Special Cells

Special Cells

Here are the description of the cells used during Physical design.

• Tap cells

• Tie cells

• 
  Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground.In Lower technology nodes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce
  These cells are part of standard-cell library
  The cells which require Vdd (Typically constant signals tied to 1) connect to Tie high cells
  The cells which require Vss/Gnd (Typically constant signals tied to 0) connect to Tie Low cells

• Endcap cells

• Decap cells.

In cross coupled design (Figure A), the drain of the PMOS connects to the gate of the NMOS, whereas the drain of the NMOS is tied to the gate of the PMOS.Both transistors in this design are still in the linear region. In the standard decap design, the gates of the transistors are directly connected to either VDD or VSS, depending on the transistor type. In this case, the gate of the NMOS device is connected to VDD through the channel resistance of the PMOS device. Similarly, the gate of the PMOS device is tied the channel resistance of the NMOS device and then connected to VSS. The added channel resistance to the gate provides the input resistance  Rin for ESD protection. The input resistance can help to limit the maximum current flow to the decap so that the voltage seen from the gate of the decap is also limited

• Spare cellsSpare cells are extra cells placed at regular interval in the chip. They are floating cells and they are placed in a group of functional cells like(and, or, nor, mux, flop, inverter, buffer).
  Once the chip is taped out and if any functional issue is found or any feature enhancement is required, these pre-placed cells can be used to add functionality without redoing the entire design.In these cased only the metal-ecos are performed and all the base layers are untouched, thus saving the cost of manufacturing.
  Some companies are using the Post mask Eco cells( special kind of cells which can be programmed to function as any gate) in their design. when not used they act as simple filler cells.If any design changes are required then these cells can be used to perform the functionality.Spare cells inputs are connected to Ground/Power when they are placed in the design and their outputs are left floating, if they are required to be used then their inputs are disconnected from VDD/GND and connected to functional logic in ECO mode.
  Spare cells are categorized mainly in two forms:
  Combinational:
  They are generally added by PNR tools and can be added using scripts in the floorplan or placement stages.
  Sequential:
  They are generally added in the RTL itself so that they can be stitched in the scan chain for testability purpose

• Tap cells