Fix transition time violations

How to fix transition time violations

Definition:

Transition time is defined by the time it takes the signal to rise from 10%(20%) to 90%(80%) of VDD is called rise time and fall from 90%(80%) to 10%(20%) of VDD is called fall time.

Rise/Fall  time: 

From where it comes:

  There are two ways the transition time constraints can be given.

   1. From user defined limit.
      set_max_transition [current_design] <value>
   2. Library specified limits.
      The .lib or .db will contain the max_transition allowed for all the standard cells.

The stringent constraints will be given preference.

Problems with transition time violations.

   1) Transition time is used to calculate the delays of the gates in the design.Tool will  extrapolate in the cases where it does not fall in the given range of the transition time specified in the Lookup table in the .lib or .db.
  If the transition time is violating the library limits then the timing calculation will not be very accurate.
  2) It will increase the Dynamic power dissipation as both nmos and pmos will be on for extended period of time.
  3) the nodes with transition time violations are more susceptible to SI issues(Crosstalk delay and noise).

Remedies.

 There are several ways to fix the transition time violations.

1) Increase the driver size.
2) Break the nets in the case of long nets.
3) Break the large fanout by duplicating drivers or with buffering.
4) Change the VT if option available(changing drivers from hvt to svt or lvt).
5) Reduce the load by downsizing the cells(special cases) after the looking the timing impact on the design.
6) Change the Load to hvt because hvt has higher lib limit.