I/P & O/P of ASIC flow

Library Preparation

Inputs required:

– Logical information of standard cells

– Physical Information of standard cells

– Technology rules

 Outputs:

– Library Milkway database

– .CEL view

Synthesis

Inputs required:

– RTL (.v or .vhdl)

– Timing constraints (.sdc or .tcl)

Outputs:

– Netlist (.v)

Design Preparation

Inputs required:

-- Netlist

-- Reference lib

Outputs:

--Milkyway database

Floorplan

Inputs required:

– Synthesised Netlist

– Physical Information of your design ( Rules for targeted technology)

– Floorplan parameters (like height, width,utilization etc.)

– Pin/Pad position

 Outputs:

– Design bonded with technology with specified area, macro placement and fixed pin placement

Powerplan

Inputs required:

– Data base with floorplan information

– Width of power rings, power straps

– Spacing between pair of VDD & VSS straps

– Spacing between VDD and VSS strap

Output:

– Design with power structure

Placement

Inputs required:

– Data base with floorplan and powerplan information

– Timing Constraints

Outputs:

– Data base with legalization placement of standard cells

– Timing reports

 – Congestion Statistics

 Clock Tree Synthesis

 Inputs required:

 – Detail placement and timing optimized database

 – Target for Latency and skew

 – Buffers that needs to be used for building up clock tree

 Outputs:

 – Legally placed Data base with Clock tree

 – Timing reports

 – Clock tree report

 – Skew report

 Routing

 Inputs required:

 – Legally placed database with clock tree structure

 Outputs:

 – Detailed routed database