ASIC PD interview questions

ASIC physical design basic interview question answers

1.  ASIC design flow.
2.  Inputs/outputs of the ASIC design flow.
3.  What is synthesis?
4.  What is clock jitter ?
5.  What are the timing optimization techniques used in Synthesis?
6.  Macro placement guidelines.
7.  How to decide floorplan size and shape, pin placement?
8.  What are the important checks after placement?
9.  What is congestion ? how to reduce the congestion?
10.  What is the difference between HFN and CTS?
11.  What is skew and latency?
12.  How to achieve skew and latency targets?
13. Which is more preffered in CTS? buffers or inverters?
14.  How to optimize the max_tran, max_cap violations.
15. Clock balancing with generated clocks.
16. Handle asynchronous clocks during CTS.
17. SI issues, Crosstalk delay, crosstalk noise,
18. What is NDR (Non-Default rule) ? How DRC will be affected due to NDR? Can you relax NDR to resolve DRC's?
19.  Which are the DFM issues?
20.  What is random variation and systematic variation?
21.  What is OCV and how derates will be applied for hold analysis?
22. Multi VT, advantages/ disadvantages of different VTs.?
23.  Timing optimization techniques?
24.  What is wire spreading? What will you loose using wire spreading?
25.  What are the DRC's you see in PnR and sign-off phases?
26. What is Recovery and Removal Time ?
27. why minimum spacing is required between two metal wires? If this kind of violations occurs then what happens?

ASIC physical design Advanced interview question answers

   

1. Have you done custom CTS ? How you approach?
2. Floor planning,Die size estimation,Macro placement.
3. If you have some output pin and clock sinks what all you take care? 
4. What is grid based routing and non grid based routing?
5. What is antenna violation? Flow to fix it? Why antenna diode in reverse bias?
6. data pulse violation, difference in glitch and data pulse,min pulse width.
7. What is max cap and max fan out? what is it is relaxed?
8. Which type of timing sign-off you are doing? (static / dynamic) 
9. Is it possible to get good results due to SI?
10. What is double switching?
11. How to debug Shorts due to Ground connection.
12. What is min pulse width violation.
13. If design is in final tapout stage how will you resolve violation if they are due SI effects.
14. If there is cloning of flop what can be issue in LEC and how to resolve it.
15. Any special timing fix where any special solution was done.
16. What is ESD violation. What is used for ESD violation.
17. What is Latchup DRC and how is it resolved.
18. What is ERC and which violation is considered in ERC.
19. What are DFM issues.
20. What is timing window and how is it prepared.
21. How static and dynamic IR drop are resolved.
22. Effect of SI on setup and hold and how.