Clock Tree Synthesis

Some Basic STA Terminologies to understand CTS effectively

Skew is the difference in arrival of clock at two consecutive pins of a sequential element.

Positive skew- If capture clockcomes late than launch clock then it is called positive skew. 

Negative skew-If capture clock comes early than launch clock it is called –ve skew. 

Local skew- It is the difference in arrival of clock at two consecutive pins of a sequential element. 

Global skew- It is Defined as the difference between max insertion delay and the min insertion delay of any flops. 

Boundary skew-It is defined as the difference between max insertion delay and the min insertion delay of boundary flops. 

Useful skew-If clock is skewed intentionally to resolve violations, it is called useful skew.

Latency- Latency is the delay of the clock source and clock network delay.

Source latency- The delay from the clock origin point to the clock definition point in the design.

Network latency- The delay from the clock definition point to the clock pin of the register.

Uncertainity- Clock uncertainty is the time difference between the arrivals of clock signals at registers in one clock domain or between domains.

Basically it is the margin including skew and jitter

Jitter- Jitter is the short-term variations of a signal with respect to its ideal position in time.

It is the variation of the clock period from edge to edge.

What is CTS

CTS basically develops the interconnect that connect the system clock to all the cells in the chip.

When CTS

CTS is performed after placement as after placement stage only all the standard cells are legalized.

Why CTS

CTS is performed after placement as after placement stage only all the standard cells are legalized.

Mainly the goals of CTS are :

1)Minimizing Clock skew
2)Minimizing Insertion delay
3)Minimizing power dissipation

Inputs required for CTS:

-- Detailed placement database

-- Target for latency and skew if specified

-- Buffers or Inverters (specific) for building the clock tree

Output:

Database with properly build clock tree in the design

Checklist after CTS:

-- Timing Reports for setup and hold

-- Clock tree report

-- Skew report

-- Power & Area report