ASIC Physical design

Saturday, 18 August 2012

Low Power design


Posted by RakeshParmar at 11:13
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Blog Archive

  • ▼  2012 (20)
    • ▼  August (20)
      • ASIC PD interview questions
      • ASIC Design Flow
      • I/P & O/P of ASIC flow
      • Fix transition time violations
      • Electrical Rule Check
      • Antenna
      • Static Timing Analysis
      • Clock Tree Synthesis
      • Electromigration
      • Crosstalk
      • Latch up violation
      • Special Cells
      • Low Power design
      • Advanced OCV
      • Timing Optimization Techniques
      • Logic Synthesis
      • Product binning
      • SSTA
      • double patterning
      • EUV

Contributors

  • Chirag Panchal
  • Khushbu
  • Meenakshi Jadon
  • Purnima Rao
  • RakeshParmar
  • Ratan Devpura
  • adarad
  • karan
  • manish garg
  • nayan navadiya
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