ASIC Physical design

Saturday, 18 August 2012

Latch up violation


Latch up in CMOS


Please refere the below link on Wikipedia for detailed explanation of Latch up.

Latch up problem in CMOS


Posted by RakeshParmar at 11:04
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Blog Archive

  • ▼  2012 (20)
    • ▼  August (20)
      • ASIC PD interview questions
      • ASIC Design Flow
      • I/P & O/P of ASIC flow
      • Fix transition time violations
      • Electrical Rule Check
      • Antenna
      • Static Timing Analysis
      • Clock Tree Synthesis
      • Electromigration
      • Crosstalk
      • Latch up violation
      • Special Cells
      • Low Power design
      • Advanced OCV
      • Timing Optimization Techniques
      • Logic Synthesis
      • Product binning
      • SSTA
      • double patterning
      • EUV

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